A highly accurate virtual physics laboratory, interactive circuit analyzer, signal oscilloscope simulation, and RLC bode frequency analyzer.
Lead Developer & Systems Architect
Computer Engineering, Signal Analysis & System Controls
Select a primary logic block model. Toggle the wire switch inputs on the schematic grid to trace state propagation in real-time.
| IN A | IN B | SUM (S) | CARRY (C) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
| D0 | D1 | SEL (S) | OUT (Y) |
|---|---|---|---|
| 0 | X | 0 | 0 |
| 1 | X | 0 | 1 |
| X | 0 | 1 | 0 |
| X | 1 | 1 | 1 |
| SET (S) | RESET (R) | Q (Next) | ~Q (Next) |
|---|---|---|---|
| 0 | 0 | LATCHED | LATCHED |
| 1 (Pulse) | 0 | 1 | 0 |
| 0 | 1 (Pulse) | 0 | 1 |
| 1 (Pulse) | 1 (Pulse) | 0 (Invalid) | 0 (Invalid) |
This plot demonstrates a classic Series RLC bandpass filter magnitude sweep. At the resonant peak , inductive reactance and capacitive reactance cancel out ($X_L = X_C$), leaving network impedance purely resistive ($Z=R$), which allows maximum current flow and unity output voltage gain.
Definitions, rigorous formulas, SI units, and structural truth tables for the workspace lab parameters.
The measure of opposition to the flow of electric current through a conductive channel, causing electrical energy dissipation as heat.
The property of an electrical conductor to oppose changes in the electric current flowing through it by storing energy in a localized magnetic field.
The ability of a system to store an electric charge configuration within an electrostatic field generated between two conductors.
The specific frequency where the inductive reactance matches the capacitive reactance magnitude ($X_L = X_C$), resulting in minimum impedance.
A measure of the sharpness of resonance. It evaluates the ratio of stored energy to power dissipated per cycle within the resonator.
A system constant describing how oscillation amplitude decays over time following an impulse excitation.
| Input A | Input B | Output (Y) |
|---|---|---|
A combinational circuit that adds two single binary bits $A$ and $B$. It outputs a Sum ($S$) using an XOR gate, and a Carry-out ($C$) using an AND gate. It does not accommodate carry inputs from preceding adder stages.
A dynamic routing switch. Based on the state of Select line $S$, it channels either input $D_0$ (when $S=0$) or input $D_1$ (when $S=1$) to output $Y$. It represents the hardware implementation of program conditional routing logic.
An asynchronous, bi-stable feedback system. Pulsing Set ($S$) forces output $Q$ high, whereas pulsing Reset ($R$) clears it. When inputs decay back to $0$, the cross-coupled loops preserve the state, acting as a single-bit latch memory block.